Guide library

All Guides

Short, checklist-driven notes for physical design study, implementation review, and interview preparation.

Foundations

Device behavior, modeling concepts, and vocabulary that support later implementation and timing decisions.

CMOS Fundamentals

A rewritten foundation guide covering semiconductor behavior, PN junction intuition, MOS structures, inverter behavior, power, and timing concepts with direct relevance to later PD and STA decisions.

Beginner | ~45 min | Updated 2026-02-18

Logic & Handoff

RTL-to-netlist concepts, optimization strategies, and handoff quality checks before physical design.

Logic Synthesis

A practical synthesis guide that covers flow stages, optimization logic, technology mapping, and handoff checks, rewritten for implementation-focused study rather than textbook sequencing.

Intermediate | ~50 min | Updated 2026-02-18

Advanced Logic Synthesis

An advanced synthesis lab note covering physical-aware optimization, CCD, multibit banking, SAIF-driven power reduction, and Boolean transforms, rewritten as a decision guide for implementation handoff quality.

Advanced | ~60 min | Updated 2026-02-18

Inputs & Setup

Required files, constraints, and setup checks that reduce downstream debug noise.

Physical Design Inputs

A setup-focused guide to PD inputs and library ecosystems, covering netlists, SDC, LEF and LIB, tech files, DEF, parasitics, power intent, and tool database setup with a practical startup checklist.

Beginner | ~40 min | Updated 2026-02-18

Implementation Flow

Floorplan, placement, and clocking notes with a practical checklist-driven review approach.

Floorplanning

A floorplanning field note focused on decision quality: die and core sizing, aspect ratio, macro placement, halos and blockages, power planning, and early congestion and timing risk management.

Intermediate | ~50 min | Updated 2026-02-18

Placement

A placement guide organized around execution checkpoints: inputs, prechecks, global placement, legalization, detailed placement, congestion and timing analysis, and preparation for CTS and routing.

Intermediate | ~50 min | Updated 2026-02-18

Clock Tree Synthesis

A CTS guide reframed around clock-distribution decisions, covering metrics, workflow, clock architectures, low-power techniques, constraints, hierarchical CTS, and advanced-node physical risks.

Intermediate | ~55 min | Updated 2026-02-18

Lab Workspace

Case-note and reference-oriented pages kept separate from production content style.

Implementation Case Notes

A structured workspace for project-style implementation notes on the .site domain, inspired by the original project showcase but rewritten as a repeatable experiment log format.

Mixed | ~25 min | Updated 2026-02-18

Reference Index

A lab-specific reference index that replaces the original long works-cited page format with a maintenance-oriented citation workflow for .site guides and case notes.

Mixed | ~20 min | Updated 2026-02-18